As one technique of improving the operation speed of a semiconductor device, the technique of applying a stress to a channel region of a MIS transistor is known. When a silicon crystal is subjected to stress and strained, the symmetry of the band structure of the silicon crystal, which has been isotropic, collapses, and the energy levels are separated. The carrier scattering decrease and effective mass decrease by the lattice vibrations due to the energy band structure change resultantly can improve the mobility of the carriers.
In the n-channel MIS transistor, the electron mobility can be improved by applying tensile stress channel-wise. In the p-channel MIS transistor, oppositely compressive stress is applied channel-wise, the hole mobility can be improved. The p-channel MIS transistor, in which holes are carriers, has low carrier mobility in comparison with the carrier mobility of the n-channel MIS transistor, in which electrons are carriers, which much affects the operation speed when the CMOS circuit is formed. Especially improvement of the carrier mobility of the p-channel MIS transistor is expected.
FIG. 22 is a diagrammatic sectional view illustrating the structure of the p-channel MIS transistor described in, e.g., S. E. Thompson et al., “A 90-nm logic technology featuring strained-silicon”, IEEE Transaction on Electron Devices, vol. 51, pp. 1790-1797, 2004.
A gate electrode 204 is formed over a silicon substrate 200 with a gate insulating film 202 formed therebetween. The surface of the silicon substrate 200, which is immediately below the gate electrode 204 is a channel region of the transistor. In the silicon substrate 200 on both sides of the gate electrode 204, impurity diffused regions 206 are respectively formed. On the surface of the silicon substrate 200 in the regions where the impurity diffused regions 206 are formed, SiGe films 208 are buried. On the gate electrode 204 and the SiGe films 208, silicide films 210 are respectively formed.
The SiGe films 208, whose lattice constant is larger than the lattice constant of silicon, is buried in the impurity diffused regions 206, whereby a compressive stress is introduced into the SiGe film 208 in parallel to the surface of the silicon substrate 200. This further induces into the SiGe film 208 a strain which extends the lattice perpendicularly to the surface of the silicon substrate 200.
Then, in the channel region of the silicon substrate 200, which is sandwiched by the SiGe films 208, a stress which extends the lattice perpendicularly to the surface of the silicon substrate 200, drawn by the extension of the SiGe films 208. Consequently, a compressive stress can be induced in the channel region in parallel to the surface of the silicon substrate 20.
The following is another example of related art of the present invention: U.S. Pat. No. 6,621,131.
However, in the above-described semiconductor device, the strain magnitude to be applied to the channel region cannot be sufficiently large, and for further speed-up, the lattice strain to be applied to the channel region is required to be increased.